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| DRAM MODULE KMM366F400CK1 KMM366F410CK1 KMM366F400CK1 & KMM366F410CK1 EDO Mode without buffer 4M x 64 DRAM DIMM using 4Mx4, 4K & 2K Refresh, 3.3V GENERAL DESCRIPTION The Samsung KMM366F40(1)0CK1 is a 4Mx64bits Dynamic RAM high density memory module. The Samsung KMM366F40(1)0CK1 consists of sixteen CMOS 4Mx4bits DRAMs in SOJ 300mil package and one 1K/2K EEPROM for SPD in 8-pin TSSOP package mounted on a 168-pin glassepoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM366F40(1)0CK1 is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets. FEATURES * Part Identification - KMM366F400CK1 (4096 cycles/64ms Ref. SOJ) - KMM366F410CK1 (2048 cycles/32ms Ref. SOJ) * New JEDEC standard proposal without buffer * Serial Presence Detect with EEPROM * Extended Data Out Mode Operation * CAS-before-RAS Refresh capability * RAS-only and Hidden refresh capability * LVTTL compatible inputs and outputs * Single +3.3V0.3V power supply * PCB : Height(1000mil), double sided component PERFORMANCE RANGE Speed -5 -6 tRAC 50ns 60ns tCAC 13ns 15ns tRC 90ns 110ns tHPC 25ns 30ns PIN CONFIGURATIONS Pin Front Pin Front Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 *CB0 *CB1 VSS NC NC VCC W0 CAS0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 *A12 VCC VCC DU VSS OE2 RAS2 CAS2 CAS3 W2 VCC NC NC *CB2 *CB3 VSS DQ16 DQ17 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ18 DQ19 VCC DQ20 NC DU NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC NC **SDA **SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 *CB4 *CB5 VSS NC NC VCC DU CAS4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back CAS5 *RAS1 DU VSS A1 A3 A5 A7 A9 A11 *A13 VCC DU DU VSS DU *RAS3 CAS6 CAS7 DU VCC NC NC *CB6 *CB7 VSS DQ48 DQ49 Pin Back 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC **SA0 **SA1 **SA2 VCC PIN NAMES Pin Name A0 - A11 A0 - A10 DQ0 - DQ63 W0, W2 OE0, OE2 RAS0, RAS2 CAS0 - CAS7 VCC VSS NC DU **SDA **SCL **SA0 -**SA2 *CB0 - *CB7 Function Address Input(4K ref.) Address Input(2K ref.) Data In/Out Read/Write Enable Output Enable Row Address Strobe Colume Address Strobe Power(+3.3V) Ground No Connection Dont use Serial Address /Data I/O Serial Clock Address in EEPROM Check Bit * These pins are not used in this modeule. ** These pins should be NC in the system which does not support SPD. www..com NOTE : A12 is used for only KMM366F400CK1 (4K ref.) www..com DRAM MODULE FUNCTIONAL BLOCK DIAGRAM KMM366F400CK1 KMM366F410CK1 RAS0 W0 OE0 A1-A11(A10) CAS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RAS2 W2 OE2 CAS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CAS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U0 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U8 U1 U9 U2 U10 U3 U11 CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U4 CAS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CAS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U12 U5 U13 U6 U14 U7 U15 Serial PD VCC .1 or .22uF Capacitor under each DRAM Vss To all DRAMs SCL A0 A1 A2 SDA SA0 SA1 SA2 DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +150 16 50 KMM366F400CK1 KMM366F410CK1 Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3 *2 Typ 3.3 0 - Max 3.6 0 VCC+0.3*1 0.8 Unit V V V V *1 : VCC+1.3V at pulse width15ns which is measured at VCC. *2 : -1.3V at pulse width15ns which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM366F400CK1 Min - KMM366F410CK1 Min -80 -5 2.4 Max 1760 1600 16 1760 1600 1440 1280 8 1760 1600 80 5 0.4 Max 1440 1280 16 1440 1280 1280 1120 8 1440 1280 80 5 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V -80 -5 2.4 - ICC1 : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3 : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4 : Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6 : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) II(L) : Input Leakage Current (Any input 0VINVCC+0.3V, all other pins not under test=0 V) IO(L) : Output Leakage Current(Data Out is disabled, 0VVOUTVCC) VOH : Output High Voltage Level (IOH = -2mA) VOL : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle, tHPC. DRAM MODULE CAPACITANCE (TA = 25C, VCC=3.3V, f = 1MHz) Item Input capacitance[A0-A11(A10)] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0, RAS2] Input capacitance[CAS0 - CAS7] Input/Output capacitance[DQ0-DQ63] Symbol CIN1 CIN2 CIN3 CIN4 CDQ1 Min - KMM366F400CK1 KMM366F410CK1 Max 90 66 66 24 17 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=3.3V0.3V. See notes 1,2.) Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z OE to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period (8K Ref) Refresh period (4K Ref) Write command set-up time CAS to W dealy time Symbol Min -5 Max Min 110 155 50 13 25 3 3 3 2 30 50 13 38 8 20 15 5 0 10 0 8 25 0 0 0 10 10 13 8 0 8 64 32 0 36 0 40 10K 37 25 10K 13 50 3 3 3 2 40 60 15 45 10 20 15 5 0 10 0 10 30 0 0 0 10 10 15 10 0 10 64 32 10K 45 30 10K 15 50 60 15 30 90 131 -6 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns 7 7 9 9 8 8 13 4 10 3,4,10 3,4,5 3,10 3 3 6,11,12 2 Unit Note tRC tRWC tRAC tCAC tAA tCLZ tOLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tREF tWCS tCWD DRAM MODULE AC CHARACTERISTICS (0CTA70C, VCC=3.3V0.3V. See notes 1,2.) Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter RAS to W dealy time Column address to W delay time CAS precharge to W delay time CAS setup time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper page mode cycle time Hyper page mode read-modify write cycle CAS precharge time (Hyper page cycle RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width Symbol Min -5 Max Min 85 55 60 5 10 5 28 25 68 8 50 30 13 13 3 13 10 10 5 3 3 15 5 5 5 5 13 13 5 3 3 15 5 5 5 5 13 15 3 15 200K 30 77 10 60 35 73 48 53 5 10 5 KMM366F400CK1 KMM366F410CK1 -6 Max Unit ns ns ns ns ns ns 35 ns ns ns ns 200K 15 15 10 10 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 7 7 tRWD tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE 3 13 13 7,11 6,11,12 6,11 DRAM MODULE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL loads and 100pF, Voh=2.0V and Vol=0.8V. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non-restrictive operating parameter. They are inclueded in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. KMM366F400CK1 KMM366F410CK1 If tCWDtCWD(min), tRWDtRWD(min) and tAWDtAWD(min), then the cycle is a read-write cycle and the data output will contain the data read from the selected address. If neither of the above contitions are satisfied, the conition of the data out is indeterminated. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-wirte cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. tCEZ(max), tREZ(max), tWEZ(max) and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. 12. If RASgoes to high before CAS high going, the open circuit condtion of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condtion of the output is achieved by RAS high going. 13. tASC6ns DRAM MODULE READ CYCLE KMM366F400CK1 KMM366F410CK1 tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tWEZ tAA OE VIH VIL - tCEZ tOEZ tOEA DQ VOH VOL - tRAC OPEN tOLZ tCAC tCLZ tREZ DATA-OUT Dont care Undefined DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM366F400CK1 KMM366F410CK1 tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRAD tRSH tCAS tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN KMM366F400CK1 KMM366F410CK1 tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ VIH VIL - Dont care Undefined DRAM MODULE READ - MODIFY - WRITE CYCLE KMM366F400CK1 KMM366F410CK1 tRAS RAS VIH VIL - tRWC tRP tCRP CAS VIH VIL - tRCD tRAD tRAH tRSH tCAS tASR VIH VIL - tASC tCAH tCSH A ROW ADDR COLUMN ADDRESS tAWD tCWD W VIH VIL - tRWL tCWL tWP tRWD OE VIH VIL - tOEA tOLZ tCLZ tCAC tAA tRAC VALID DATA-OUT tOED tOEZ tDS tDH VALID DATA-IN DQ VI/OH VI/OL - Dont care Undefined DRAM MODULE HYPER PAGE READ CYCLE KMM366F400CK1 KMM366F410CK1 tRASP RAS VIH VIL o tRP tCSH tCRP CAS VIH VIL - tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRCD tCAS tRAD tASR A VIH VIL - tRAH tASC tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH tREZ ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tCPA tCAC tAA tCPA tCAC tOEA tCAC tAA tCPA tOCH tOEA tOEP tDOH VALID DATA-OUT tCAC tAA tCHO tOEP tAA OE VIH VIL - tCAC tRAC DQ VOH VOL - tOEA tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ tOEZ tOLZ tCLZ VALID DATA-OUT Dont care Undefined DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM366F400CK1 KMM366F410CK1 tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS o tHPC tCP tRSH tCAS tASR A VIH VIL - tRAH tCAH tASC tCAH o tASC tCAH ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS o COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP tCWL o o o tWCS tWCH tWP tCWL tRWL tWP tCWL OE VIH VIL - tDS DQ VIH VIL - tDH VALID DATA-IN tDS tDH o VALID DATA-IN tDS tDH o VALID DATA-IN Dont care Undefined DRAM MODULE HYPER PAGE READ-MODIFY-WRITE CYCLE KMM366F400CK1 KMM366F410CK1 RAS VIH VIL - tRASP tCSH tCRP tRSH tHPRWC tRCD tCAS tRAD tRAH tASR tASC COL. ADDR tRP tCP tCAS tRAL tCRP CAS VIH VIL - tCAH tASC COL. ADDR tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tCWL tWP tCWD tAWD tCPWD tOEA tOED tRWL tCWL tWP tCWD tAWD tRWD tOEA tCAC tAA tRAC tOEZ tDS tCAC OE VIH VIL - tOED tDH tAA tDH tOEZ tDS DQ VI/OH VI/OL - tCLZ tOLZ VALID DATA-OUT tCLZ VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Dont care Undefined DRAM MODULE HYPER PAGE READ AND WRITE MIXED CYCLE KMM366F400CK1 KMM366F410CK1 tRASP RAS VIH VIL READ(tCAC) READ(tCPA) WRITE READ(tAA) tRP tHPC tCP CAS VIH VIL - tHPC tCP tCP tCAS tASC COL. ADDR tHPC tCAS tASC tCAH COL. ADDR tRAD tASR tRAH tASC tCAS tCAH tCAS tCAH tCAH tASC COLUMN ADDRESS A VIH VIL - ROW ADDR COLUMN ADDRESS tRCS W VIH VIL - tRCH tRCS tRCH tWCS tWCH tRCH tWPE tCLZ tCPA OE VIH VIL - tWED DQ VI/OH VI/OL - tOEA tCAC tAA tRAC tWEZ tDH tWEZ VALID DATA-OUT tDS VALID DATA-IN tAA VALID DATA-OUT tREZ VALID DATA-OUT Dont care Undefined DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC RAS VIH VIL - KMM366F400CK1 KMM366F410CK1 tRP tRAS tCRP tRPC tCRP CAS VIH VIL - tASR A VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Dont care tRP RAS VIH VIL - tRC tRAS tRP tRPC tCP tCSR tCHR tRPC CAS VIH VIL - tWRP W VIH VIL - tWRH tCEZ DQ VOH VOL - OPEN Dont care Undefined * In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) KMM366F400CK1 KMM366F410CK1 tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRRH tWRH tWRP tAA OE VIH VIL - tOEA tOLZ tCAC tCLZ tRAC tOEZ DATA-OUT tCEZ tREZ tWEZ DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN KMM366F400CK1 KMM366F410CK1 tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP tRCD tRSH tCHR CAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWRP tWCH tWP tWRH OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE KMM366F400CK1 KMM366F410CK1 tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W OE VIH VIL VIH VIL - tWRP tWRH tRCS tAA tCAC tRRH tRCH DQ VOH VOL - tCLZ tOEA tOEZ DATA-OUT tCEZ tREZ tWEZ WRITE CYCLE W VIH VIL VIH VIL - tWRP tWRH tWCS tRWL tCWL tWCH tWP OE tDS DQ VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tRCS tAWD tCWD tCAC tWP tCWL tRWL tAA tOEA OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Dont care Undefined NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care KMM366F400CK1 KMM366F410CK1 tRP RAS VIH VIL - tRASS tRPS tRPC tCP tCSR tCHS tRPC CAS VIH VIL - tCEZ DQ VOH VOL - OPEN W VIH VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Dont care tRC tRAS tRPC tCP CAS VIH VIL - tRP RAS VIH VIL - tRP tRPC tCSR tCHR tWTS W VIH VIL - tWTH tCEZ DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE PACKAGE DIMENSIONS KMM366F400CK1 KMM366F410CK1 Units : Inches (millimeters) 5.250 (133.350) 0.118 (3.000) 5.014 (127.350) 0.054 (1.372) R 0.079 (R 2.000) 0.1570.004 (4.0000.100) 0.118 (3.000) 1.00 (25.40) .118DIA.004 (3.000DIA.100) 0.350 (8.890) 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) ( Front view ) 0.350Max (8.89Max) (5.08 Min) 0.200 Min 0.100Min (2.540Min) A B C (17.780) 0.0500.0039 (1.2700.10) ( Back view ) 0.250 (6.350) 0.250 (6.350) (2.540 Min) 0.100 Min 0.123.005 (3.125.125) 0.123.005 (3.125.125) 0.079.0040 (2.000.100) 0.079.0040 (2.000.100) 0.050 (1.270) Detail A Tolerances : .005(.13) unless otherwise specified The used device is 4Mx4 DRAM with EDO mode, SOJ DRAM Part No. : KMM366F400CK1 - KM44V4004CK KMM366F410CK1 - KM44V4104CK Revision History Rev 0.0 : Aug. 1997 Detail B Detail C 0.700 0.039.002 (1.000.050) 0.010Max (0.250 Max) |
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